An important requirement imposed on modem electronic systems having high reliability requirements (e.g., systems performing real-time and/or mission-critical operations) is that the systems hardware (e.g., digital logic circuits) must be correctly reset and initialized. In this regard, it is critical that the system designers ensure that the systems' hardware is reset or initialized correctly at power on, and subsequently is not reset again. For example, in a missile system, at system startup and prior to launch, the missile system's mission computer should verify that the systems' digital logic circuits have been reset and properly initialized. Once the mission computer verifies that such an initialization reset has occurred, the mission computer could block any subsequent reset attempts. Thus, in an ideal design, the system's software should be able to verify that an initial reset has occurred before blocking any subsequent reset attempts. However, a problem with the existing system designs is that it is possible for the software to proceed into an application mode without having properly verified that an initial reset has occurred. Consequently, the existing system designs cannot guarantee the correct initialization and operation of the digital logic circuitry or hardware involved.
For example, a reset detector circuit could be used to detect a reset and verify to application software running on a system computer that such a reset has occurred. The application software could perform this verification before proceeding with “normal” operations, and halt these operations if such a reset has not occurred. In some existing applications, in an attempt to ensure that the hardware (logic circuitry) is correctly reset and subsequent resets do not occur, the system designers have imposed a time requirement so that once the hardware has been reset initially, it must be held in a reset mode for a predetermined length of time. Notably, once a power-on reset has occurred for the hardware in a real-time, mission-critical system (e.g., spacecraft, missile, aircraft, etc.), this hardware must not be reset again, or the system's operations could be interrupted, halted and result in a mission failure. However, notwithstanding the benefits of prolonging the initial reset mode for a predetermined period of time, a problem with the existing circuitry and associated application software is that they are still incapable of blocking all subsequent reset requests from occurring. For example, noise generated in a system can cause a reset line to toggle unexpectedly (e.g., noise caused by booster separation, faulty circuitry, or other localized noise in the circuitry involved) after the prolonged reset mode is terminated. Consequently, a pressing need exists for a reset detector circuit that can verify that an initial hardware reset has occurred, that it was asserted a minimum length of time, allow no other resets to occur, and detect (e.g., for monitoring and reporting purposes) if a subsequent reset request is made. As described in detail below, the present invention provides such a reset detector circuit, which resolves the above-described reset problems and other similar problems.